Memory devices, such as flash electrically erasable programmable read only memory (EEPROM), are becoming more widespread. For example, “jump” drives (e.g., for universal serial bus (USB) connections), memory cards, and other nonvolatile memory applications are commonplace in cameras, video games, computers, and other electronic devices. FIG. 1 shows a block diagram of a conventional memory array organization 100. For example, the memory array can be organized in bits (e.g., 8-bit depth 108), bytes (e.g., 2 kB portion 104, and 64 B portion 106), pages (e.g., 512 K pages 102, corresponding to 8192 blocks), and blocks (e.g., block 110, equal to 64 pages), forming an 8 Mb device in this particular example. Also, single page 112 can be organized as portion 114 (e.g., 2 kB+64 B=2112 B=840h), and portion 116, corresponding to an eight (8)-bit wide data input/output (I/O) path (e.g., I/O 0-I/O 7).
This type of flash memory may represent a “NAND” type, which typically has faster erase and write times, higher density, lower cost per bit, and more endurance than a “NOR” type flash memory. However a NAND flash I/O interface typically allows only sequential access to data. FIG. 2A shows a timing diagram 200 for a conventional read operation. As shown below in Table 1, various pin functions can correspond to designated pins in a NAND flash interface.
TABLE 1PINPIN FUNCTIONI/O[7:0]Data in/outCLECommand latch enableALEAddress latch enableCE—Chip enableRE—Read enableWE—Write enableWP—Write protectR/B—Ready/busy output
In FIG. 2A, WE_ can be pulsed (e.g., at a 25 ns period) to allow row address (e.g., RA1, RA2, and RA3) and column address (e.g., CA1 and CA2) information to be latched in the device. Command “00h” may indicate a read address input, while command “30h” may indicate a read start, as shown. With RE_ pulsing, data Dout N, Dout N+1, Dout N+2, . . . Dout M can be read from the device. Also, signal R/B_in a low logic state can indicate a busy state on the output, and R/B_ may go high some period of time after the last rising edge of WE_, for example. Row and column address multiplexing on the data in/out pins (e.g., I/O[7:0]) can be as shown below in Table 2.
TABLE 2CYCLEI/O[0]I/O[1]I/O[2]I/O[3]I/O[4]I/O[5]I/O[6]I/O[7]1st Cycle:A0A1A2A3A4A5A6A7Column Address2nd Cycle:A8A9A10A11LLLLColumn Address3rd Cycle:A12A13A14A15A16A17A18A19Row Address4th Cycle:A20A21A22A23A24A25A26A27Row Address5th Cycle:A28A29A30LLLLLRow Address
For example, higher address bits can be utilized for addressing larger memory arrangements (e.g., A30 for 2 Gb, A31 for 4 Gb, A32 for 8 Gb, A33 for 16 Gb, A34 for 32 Gb, and A35 for 64 Gb).
Referring now to FIG. 2B, a timing diagram 220 shows a conventional page program operation. Here, command “80h” can indicate serial data (e.g., Din N . . . Din M) input. Command “10h” can indicate an auto program, followed by a status read (command “70h”). I/O[0]=“0” can indicate no error condition, while I/O[0]=“1” may indicate that an error in auto programming has occurred. Also, signal R/B_may be low, indicating a busy state, for a length of time typically on the order of hundreds of μs. Also, a rising edge of RE_can trail a rising edge of WE_by a period of time (60 ns, in one example).
FIG. 2C shows a timing diagram 240 for a conventional block erase operation. Here, command “60h” can indicate a block erase operation, with sequential row addresses (e.g., RA1, RA2, and RA3) supplied. Command “D0h” can indicate a cycle 2 block erase operation. The block erase operation can be checked by a status read (command “70h”), where I/O[0]=“0” can indicate no error condition, while I/O[0]=“1” may indicate that an error in block erase has occurred. Example signal times can include signal R/B_ being low for a period of time typically on the order of about a millisecond (with a predetermined maximum), a rising edge of RE_ trailing a rising edge of WE_, and a rising edge of WE corresponding to the D0h command to a falling edge of R/B_ of about 100 ns.
In conventional flash memory arrangements involving multiple chips or devices in a common package (e.g., a hybrid drive), multiple chip enable (CE_) pins may be required to access the various flash memory chips. Particularly in larger memory structures, such multiple enable pins may result in relatively complicated control logic and consume a relatively large chip area. Therefore, it would be desirable to provide a solution that is able to control access to (e.g., programming and reading) multiple flash memory chips or devices without increasing the pin count.